Additional Information
Book Details
Abstract
Since the publication of the first edition, a new version of the VHDL standard has been agreed and analogue extensions to the language have also been adopted. The second edition of Digital System Design with VHDL includes additions in two important areas; sections on writing testbenches have been added to relevant chapters, and the addition of a new chapter on VHDL-AMS and mixed-signal modeling. The unique approach will be appreciated by undergraduates in Electronic Engineering and Computer Engineering in all years of their courses and by students undertaking postgraduate study. There is also a proven need from industry for graduates with knowledge of VHDL and the associated design tools and this book will be an asset to engineers who wish to continue their studies.
Table of Contents
| Section Title | Page | Action | Price |
|---|---|---|---|
| Cover | Cover | ||
| Digital System Design with VHDL | i | ||
| Contents | v | ||
| Preface | ix | ||
| Introduction | 1 | ||
| Modern digital design | 1 | ||
| CMOS technology | 5 | ||
| Programmable logic | 10 | ||
| Electrical properties | 14 | ||
| Summary | 18 | ||
| Further reading | 18 | ||
| Exercises | 18 | ||
| Combinational logic design | 19 | ||
| Boolean algebra | 19 | ||
| Logic gates | 22 | ||
| Combinational logic design | 22 | ||
| Timing | 30 | ||
| Number codes | 32 | ||
| Summary | 36 | ||
| Further reading | 36 | ||
| Exercises | 36 | ||
| Combinational logic using VHDL gate models | 38 | ||
| Entities and architectures | 38 | ||
| Identifiers, spaces and comments | 40 | ||
| Netlists | 41 | ||
| Signal assignments | 44 | ||
| Generics | 45 | ||
| Constant and open ports | 47 | ||
| Testbenches | 48 | ||
| Configurations | 48 | ||
| Summary | 51 | ||
| Further reading | 51 | ||
| Exercises | 51 | ||
| Combinational building blocks | 53 | ||
| Three-state buffers | 53 | ||
| Decoders | 58 | ||
| Multiplexers | 64 | ||
| Priority encoder | 66 | ||
| Adders | 69 | ||
| Parity checker | 72 | ||
| Testbenches for combinational blocks | 75 | ||
| Summary | 78 | ||
| Further reading | 78 | ||
| Exercises | 78 | ||
| Synchronous sequential design | 80 | ||
| Synchronous sequential systems | 80 | ||
| Models of synchronous sequential systems | 81 | ||
| Algorithmic state machines | 85 | ||
| Synthesis from ASM charts | 89 | ||
| State machines in VHDL | 99 | ||
| VHDL testbenches for state machines | 109 | ||
| Summary | 111 | ||
| Further reading | 112 | ||
| Exercises | 112 | ||
| VHDL models of sequential logic blocks | 115 | ||
| Latches | 115 | ||
| Flip-flops | 119 | ||
| JK and T flip-flops | 128 | ||
| Registers and shift registers | 132 | ||
| Counters | 135 | ||
| Memory | 143 | ||
| Sequential multiplier | 147 | ||
| Testbenches for sequential building blocks | 150 | ||
| Summary | 153 | ||
| Further reading | 154 | ||
| Exercises | 154 | ||
| Complex sequential systems | 156 | ||
| Linked state machines | 156 | ||
| Datapath/controller partitioning | 160 | ||
| Instructions | 162 | ||
| A simple microprocessor | 163 | ||
| VHDL model of a simple microprocessor | 167 | ||
| Summary | 176 | ||
| Further reading | 177 | ||
| Exercises | 177 | ||
| VHDL simulation | 178 | ||
| Event-driven simulation | 178 | ||
| Simulation of VHDL models | 182 | ||
| Simulation modelling issues | 185 | ||
| File operations | 186 | ||
| Summary | 188 | ||
| Further reading | 188 | ||
| Exercises | 188 | ||
| VHDL synthesis | 190 | ||
| RTL synthesis | 191 | ||
| Constraints | 203 | ||
| Synthesis for FPGAs | 206 | ||
| Behavioural synthesis | 209 | ||
| Verifying synthesis results | 216 | ||
| Summary | 218 | ||
| Further reading | 218 | ||
| Exercises | 218 | ||
| Testing digital systems | 221 | ||
| The need for testing | 221 | ||
| Fault models | 222 | ||
| Fault-oriented test pattern generation | 224 | ||
| Fault simulation | 231 | ||
| Fault simulation in VHDL | 235 | ||
| Summary | 244 | ||
| Further reading | 245 | ||
| Exercises | 245 | ||
| Design for testability | 248 | ||
| Ad hoc testability improvements | 249 | ||
| Structured design for test | 249 | ||
| Built-in self-test | 252 | ||
| Boundary scan (IEEE 1149.1) | 260 | ||
| Summary | 268 | ||
| Further reading | 268 | ||
| Exercises | 268 | ||
| Asynchronous sequential design | 271 | ||
| Asynchronous circuits | 271 | ||
| Analysis of asynchronous circuits | 274 | ||
| Design of asynchronous sequential circuits | 278 | ||
| Asynchronous state machines | 286 | ||
| Setup and hold times and metastability | 290 | ||
| Summary | 297 | ||
| Further reading | 298 | ||
| Exercises | 298 | ||
| Interfacing with the analogue world | 301 | ||
| Digital to analogue converters | 302 | ||
| Analogue to digital converters | 303 | ||
| VHDL-AMS | 306 | ||
| Phased-locked loops | 315 | ||
| VHDL-AMS simulators | 319 | ||
| Summary | 321 | ||
| Further reading | 321 | ||
| Exercises | 321 | ||
| Appendix A VHDL standards | 322 | ||
| Appendix B Verilog | 327 | ||
| Appendix C Shared variable packages | 333 | ||
| Bibliography | 339 | ||
| Answers to selected exercises | 341 | ||
| Index | 363 |