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Book Details
Abstract
For all courses in digital electronics, from introductory through advanced. Like previous editions, this text will be used widely in technology classes ranging from high schools and two-year programs to four-year engineering, engineering technology, and computer science programs.
Take a journey in Digital Systems from novice to expert.
Written for all courses in digital electronics–from introductory to advanced, from high school to two- and four-year college programs–this Twelfth Edition of Digital Systems thoroughly prepares students for the study of digital systems and computer and microcontroller hardware. The text begins with the basics of digital systems, including the AHDL hardware description language, then gradually progresses to increasingly challenging topics, including the more complex VHDL.
The text is comprehensive yet highly readable, clearly introducing the purpose and fundamentals of each topic before delving into more technical descriptions. It is also definition-focused, with new terms listed in each chapter and defined in a glossary. This Twelfth Edition has been thoroughly revised and updated with new material on section-level learning outcomes, Quadrature Shaft Encoders used to obtain absolute shaft positions, troubleshooting prototype circuits using systematic fault isolation techniques, Time Division Multiplexing, expanded discussion of VHDL data objects and more!
Table of Contents
| Section Title | Page | Action | Price |
|---|---|---|---|
| Cover | Cover | ||
| Title Page | 1 | ||
| Copyright Page | 2 | ||
| Preface | 3 | ||
| Contents | 11 | ||
| Chapter 1 Introductory Concepts | 22 | ||
| 1-1 Introduction to Digital 1s and 0s | 24 | ||
| 1-2 Digital Signals | 29 | ||
| Need for Timing | 30 | ||
| Highs and Lows Over Time | 31 | ||
| Periodic/Aperiodic | 31 | ||
| Period/Frequency | 31 | ||
| Duty Cycle | 32 | ||
| Transitions | 32 | ||
| Edges/Events | 32 | ||
| 1-3 Logic Circuits and Evolving Technology | 33 | ||
| Logic Circuits | 33 | ||
| Digital Integrated Circuits | 34 | ||
| 1-4 Numerical Representations | 34 | ||
| Analog Representations | 35 | ||
| Digital Representations | 35 | ||
| 1-5 Digital and Analog Systems | 37 | ||
| Advantages of Digital Techniques | 37 | ||
| Limitations of Digital Techniques | 38 | ||
| 1-6 Digital Number Systems | 39 | ||
| Decimal System | 39 | ||
| Decimal Counting | 40 | ||
| Binary System | 41 | ||
| Binary Counting | 42 | ||
| 1-7 Representing Signals with Numeric Quantities | 43 | ||
| 1-8 Parallel and Serial Transmission | 45 | ||
| 1-9 Memory | 47 | ||
| 1-10 Digital Computers | 48 | ||
| Major Parts of a Computer | 48 | ||
| Types of Computers | 49 | ||
| Memory | 50 | ||
| Digital Progress Today and Tomorrow | 51 | ||
| Chapter 2 Number Systems and Codes | 56 | ||
| 2-1 Binary-to-Decimal Conversions | 58 | ||
| 2-2 Decimal-to-Binary Conversions | 59 | ||
| Counting Range | 61 | ||
| 2-3 Hexadecimal Number System | 61 | ||
| Hex-to-Decimal Conversion | 62 | ||
| Decimal-to-Hex Conversion | 63 | ||
| Hex-to-Binary Conversion | 63 | ||
| Binary-to-Hex Conversion | 64 | ||
| Counting in Hexadecimal | 64 | ||
| Usefulness of Hex | 64 | ||
| Summary of Conversions | 65 | ||
| 2-4 BCD Code | 66 | ||
| Binary-Coded-Decimal Code | 66 | ||
| Comparison of BCD and Binary | 67 | ||
| 2-5 The Gray Code | 68 | ||
| Quadrature Encoders | 70 | ||
| 2-6 Putting it All Together | 71 | ||
| 2-7 The Byte, Nibble, and Word | 72 | ||
| Bytes | 72 | ||
| Nibbles | 72 | ||
| Words | 73 | ||
| 2-8 Alphanumeric Codes | 73 | ||
| ASCII Code | 74 | ||
| 2-9 Parity Method For Error Detection | 76 | ||
| Parity Bit | 77 | ||
| Error Correction | 78 | ||
| 2-10 Applications | 79 | ||
| Chapter 3 Describing Logic Circuits | 88 | ||
| 3-1 Boolean Constants and Variables | 91 | ||
| 3-2 Truth Tables | 92 | ||
| 3-3 OR Operation with OR Gates | 93 | ||
| OR Gate | 94 | ||
| Summary of the OR Operation | 95 | ||
| 3-4 AND Operation with AND Gates | 97 | ||
| AND Gate | 98 | ||
| Summary of the AND Operation | 99 | ||
| 3-5 NOT Operation | 100 | ||
| NOT Circuit (INVERTER) | 101 | ||
| Summary of Boolean Operations | 101 | ||
| 3-6 Describing Logic Circuits Algebraically | 102 | ||
| Operator Precedence | 102 | ||
| Circuits Containing INVERTERs | 103 | ||
| 3-7 Evaluating Logic-Circuit Outputs \r | 104 | ||
| Analysis Using a Table | 105 | ||
| 3-8 Implementing Circuits from Boolean Expressions | 107 | ||
| 3-9 NOR Gates and NAND Gates \r | 108 | ||
| NOR Gate | 108 | ||
| NAND Gate | 110 | ||
| 3-10 Boolean Theorems | 112 | ||
| Multivariable Theorems | 113 | ||
| 3-11 DeMorgan’s Theorems | 115 | ||
| Implications of DeMorgan’s Theorems | 117 | ||
| 3-12 Universality of NAND Gates and NOR Gates | 119 | ||
| 3-13 Alternate Logic-Gate Representations | 122 | ||
| Logic-Symbol Interpretation | 124 | ||
| Summary | 124 | ||
| 3-14 Which Gate Representation to Use | 125 | ||
| Which Circuit Diagram Should Be Used? | 127 | ||
| Bubble Placement | 127 | ||
| Analyzing Circuits | 128 | ||
| Asserted Levels | 130 | ||
| Labeling Active-LOW Logic Signals | 130 | ||
| Labeling Bistate Signals | 130 | ||
| 3-15 Propagation Delay | 131 | ||
| 3-16 Summary of Methods to Describe Logic Circuits | 132 | ||
| 3-17 Description Languages Versus Programming Languages | 134 | ||
| VHDL and AHDL | 135 | ||
| Computer Programming Languages | 135 | ||
| 3-18 Implementing Logic Circuits with PLDs | 137 | ||
| 3-19 HDL Format and Syntax | 138 | ||
| 3-20 Intermediate Signals | 141 | ||
| Chapter 4 Combinational Logic Circuits | 156 | ||
| 4-1 Sum-of-Products Form | 158 | ||
| Product-of-Sums | 158 | ||
| 4-2 Simplifying Logic Circuits | 159 | ||
| 4-3 Algebraic Simplification | 160 | ||
| 4-4 Designing Combinational Logic Circuits | 165 | ||
| Complete Design Procedure | 167 | ||
| 4-5 Karnaugh Map Method | 172 | ||
| Karnaugh Map Format | 172 | ||
| Looping | 174 | ||
| Looping Groups of Two (Pairs) | 174 | ||
| Looping Groups of Four (Quads) | 175 | ||
| Looping Groups of Eight (Octets) | 176 | ||
| Complete Simplification Process | 177 | ||
| Filling a K Map from an Output Expression | 180 | ||
| Don’t-Care Conditions | 181 | ||
| Summary | 183 | ||
| 4-6 Exclusive-OR and Exclusive-NOR Circuits | 183 | ||
| Exclusive-OR | 183 | ||
| Exclusive-NOR | 185 | ||
| 4-7 Parity Generator and Checker | 189 | ||
| 4-8 Enable/Disable Circuits | 190 | ||
| 4-9 Basic Characteristics of Legacy Digital ICs | 193 | ||
| Bipolar and Unipolar Digital ICs | 194 | ||
| TTL Family | 195 | ||
| CMOS Family | 196 | ||
| Power and Ground | 196 | ||
| Logic-Level Voltage Ranges | 197 | ||
| Unconnected (Floating) Inputs | 197 | ||
| Logic-Circuit Connection Diagrams | 198 | ||
| 4-10 Troubleshooting Digital Systems | 200 | ||
| 4-11 Internal Digital IC Faults | 202 | ||
| Malfunction in Internal Circuitry | 202 | ||
| Input Internally Shorted to Ground or Supply | 202 | ||
| Output Internally Shorted to Ground or Supply | 203 | ||
| Open-Circuited Input or Output | 203 | ||
| Short Between Two Pins | 205 | ||
| 4-12 External Faults | 206 | ||
| Open Signal Lines | 206 | ||
| Shorted Signal Lines | 207 | ||
| Faulty Power Supply | 207 | ||
| Output Loading | 208 | ||
| 4-13 Troubleshooting Prototyped Circuits | 210 | ||
| 4-14 Programmable Logic Devices | 214 | ||
| PLD Hardware | 215 | ||
| Programming a PLD | 216 | ||
| Development Software | 217 | ||
| Design and Development Process | 220 | ||
| 4-15 Representing Data in HDL | 222 | ||
| Bit Arrays/Bit Vectors | 223 | ||
| Ahdl Bit Array Declarations | 224 | ||
| 4-16 Truth Tables Using Hdl | 227 | ||
| 4-17 Decision Control Structures in HDL | 230 | ||
| IF/ELSE | 231 | ||
| ELSIF | 235 | ||
| Chapter 5 Flip-Flops and Related Devices | 256 | ||
| 5-1 NAND Gate Latch | 259 | ||
| Setting the Latch (FF) | 260 | ||
| Resetting the Latch (FF) | 260 | ||
| Simultaneous Setting and Resetting | 261 | ||
| Summary of NAND Latch | 261 | ||
| Alternate Representations | 262 | ||
| Terminology | 262 | ||
| 5-2 NOR Gate Latch | 265 | ||
| Flip-Flop State on Power-Up | 267 | ||
| 5-3 Troubleshooting Case Study | 267 | ||
| 5-4 Digital Pulses | 269 | ||
| 5-5 Clock Signals and Clocked Flip-Flops | 271 | ||
| Clocked Flip-Flops | 272 | ||
| Setup and Hold Times | 272 | ||
| 5-6 Clocked S-R Flip-Flop | 274 | ||
| Internal Circuitry of the Edge-Triggered S-R Flip-Flop | 276 | ||
| 5-7 Clocked J-K Flip-Flop | 278 | ||
| Internal Circuitry of the Edge-Triggered J-K Flip-Flop | 279 | ||
| 5-8 Clocked D Flip-Flop | 280 | ||
| Implementation of the D Flip-Flop | 281 | ||
| Parallel Data Transfer | 282 | ||
| 5-9 D Latch (Transparent Latch) | 282 | ||
| 5-10 Asynchronous Inputs | 284 | ||
| Designations for Asynchronous Inputs | 286 | ||
| 5-11 Flip-Flop Timing Considerations | 287 | ||
| Setup and Hold Times | 287 | ||
| Propagation Delays | 288 | ||
| Maximum Clocking Frequency, fMAX | 288 | ||
| Clock Pulse HIGH and LOW Times | 288 | ||
| Asynchronous Active Pulse Width | 289 | ||
| Clock Transition Times | 289 | ||
| 5-12 Potential Timing Problem in FF Circuits | 289 | ||
| 5-13 Flip-Flop Applications | 291 | ||
| 5-14 Flip-Flop Synchronization | 292 | ||
| 5-15 Detecting an Input Sequence | 293 | ||
| 5-16 Detecting a Transition or “Event” | 295 | ||
| 5-17 Data Storage and Transfer | 296 | ||
| Parallel Data Transfer | 297 | ||
| 5-18 Serial Data Transfer: Shift Registers | 298 | ||
| Hold Time Requirement | 299 | ||
| Serial Transfer Between Registers | 300 | ||
| Shift-Left Operation | 301 | ||
| Parallel Versus Serial Transfer | 301 | ||
| 5-19 Frequency Division and Counting | 302 | ||
| Counting Operation | 303 | ||
| State Transition Diagram | 304 | ||
| MOD Number | 304 | ||
| 5-20 Application of Flip-Flops with Timing Constraints | 306 | ||
| Timing Issues | 310 | ||
| 5-21 Microcomputer Application | 313 | ||
| 5-22 Schmitt-Trigger Devices | 314 | ||
| 5-23 One-Shot (Monostable Multivibrator) | 316 | ||
| Nonretriggerable One-Shot | 316 | ||
| Retriggerable One-Shot | 317 | ||
| Actual Devices | 318 | ||
| Monostable Multivibrator | 318 | ||
| 5-24 Clock Generator Circuits | 319 | ||
| Schmitt-Trigger Oscillator | 319 | ||
| 555 Timer Used as an Astable Multivibrator | 319 | ||
| Crystal-Controlled Clock Generators | 322 | ||
| 5-25 Troubleshooting Flip-Flop Circuits | 322 | ||
| Open Inputs | 323 | ||
| Shorted Outputs | 324 | ||
| Clock Skew | 325 | ||
| 5-26 Sequential Circuits in PLDs Using Schematic Entry | 327 | ||
| 5-27 Sequential Circuits Using HDL | 331 | ||
| The D Latch | 334 | ||
| 5-28 Edge-Triggered Devices | 335 | ||
| 5-29 HDL Circuits with Multiple Components | 340 | ||
| Chapter 6 Digital Arithmetic: Operations and Circuits | 360 | ||
| 6-1 Binary Addition and Subtraction | 362 | ||
| Binary Addition | 362 | ||
| Binary Subtraction | 363 | ||
| 6-2 Representing Signed Numbers | 363 | ||
| 1’s-Complement Form | 364 | ||
| 2’s-Complement Form | 365 | ||
| Representing Signed Numbers Using 2’s Complement | 365 | ||
| Sign Extension | 367 | ||
| Negation | 367 | ||
| Special Case in 2’s-Complement Representation | 368 | ||
| 6-3 Addition in the 2’s-Complement System | 371 | ||
| 6-4 Subtraction in the 2’s-Complement System | 372 | ||
| Arithmetic Overflow | 373 | ||
| Number Circles and Binary Arithmetic | 374 | ||
| 6-5 Multiplication of Binary Numbers | 375 | ||
| Multiplication in the 2’s-Complement System | 376 | ||
| 6-6 Binary Division | 377 | ||
| 6-7 BCD Addition | 377 | ||
| Sum Equals 9 or Less | 378 | ||
| Sum Greater than 9 | 378 | ||
| BCD Subtraction | 379 | ||
| 6-8 Hexadecimal Arithmetic | 380 | ||
| Hex Addition | 380 | ||
| Hex Subtraction | 381 | ||
| Hex Representation of Signed Numbers | 382 | ||
| 6-9 Arithmetic Circuits | 383 | ||
| Arithmetic/Logic Unit | 383 | ||
| 6-10 Parallel Binary Adder | 384 | ||
| 6-11 Design of a Full Adder | 386 | ||
| K-Map Simplification | 388 | ||
| Half Adder | 389 | ||
| 6-12 Complete Parallel Adder with Registers | 389 | ||
| Register Notation | 390 | ||
| Sequence of Operations | 391 | ||
| 6-13 Carry Propagation | 392 | ||
| 6-14 Integrated-Circuit Parallel Adder | 393 | ||
| Cascading Parallel Adders | 393 | ||
| 6-15 2’s-Complement Circuits | 395 | ||
| Addition | 395 | ||
| Subtraction | 395 | ||
| Combined Addition and Subtraction | 397 | ||
| 6-16 ALU Integrated Circuits | 398 | ||
| The 74LS382/74HC382 ALU | 399 | ||
| Expanding the ALU | 401 | ||
| Other ALUs | 402 | ||
| 6-17 Troubleshooting Case Study | 402 | ||
| 6-18 Using Altera Library Functions | 404 | ||
| Megafunction LPMs for Arithmetic Circuits | 405 | ||
| Using a Parallel Adder to Count | 409 | ||
| 6-19 Logical Operations on Bit Arrays with HDLs | 410 | ||
| 6-20 HDL Adders | 412 | ||
| 6-21 Parameterizing the Bit Capacity of a Circuit | 414 | ||
| Chapter 7 Counters and Registers | 428 | ||
| 7-1 Asynchronous (Ripple) Counters | 430 | ||
| Signal Flow | 431 | ||
| MOD Number | 432 | ||
| Frequency Division | 432 | ||
| Duty Cycle | 433 | ||
| 7-2 Propagation Delay in Ripple Counters | 434 | ||
| 7-3 Synchronous (Parallel) Counters | 436 | ||
| Circuit Operation | 438 | ||
| Advantage of Synchronous Counters over Asynchronous | 438 | ||
| Actual ICs | 438 | ||
| 7-4 Counters with Mod Numbers <2N | 439 | ||
| State Transition Diagram | 441 | ||
| Displaying Counter States | 441 | ||
| Changing the MOD Number | 443 | ||
| General Procedure | 443 | ||
| Decade Counters/BCD Counters | 445 | ||
| 7-5 Synchronous Down and Up/Down Counters | 446 | ||
| 7-6 Presettable Counters | 448 | ||
| Synchronous Presetting | 450 | ||
| 7-7 IC Synchronous Counters | 450 | ||
| The 74ALS160-163/74HC160-163 Series | 450 | ||
| The 74ALS190-191/74HC190-191 Series | 454 | ||
| Multistage Arrangement | 459 | ||
| 7-8 Decoding a Counter | 460 | ||
| Active-HIGH Decoding | 461 | ||
| Active-LOW Decoding | 462 | ||
| BCD Counter Decoding | 462 | ||
| 7-9 Analyzing Synchronous Counters | 464 | ||
| 7-10 Synchronous Counter Design | 467 | ||
| Basic Idea | 467 | ||
| J-K Excitation Table | 468 | ||
| Design Procedure | 469 | ||
| Stepper Motor Control | 472 | ||
| Synchronous Counter Design with D FF | 474 | ||
| 7-11 Altera Library Functions for Counters | 476 | ||
| 7-12 HDL Counters | 480 | ||
| State Transition Description Methods | 481 | ||
| Behavioral Description | 484 | ||
| Simulation of Basic Counters | 487 | ||
| Full-Featured Counters in HDL | 487 | ||
| Simulation of Full-Featured Counter | 491 | ||
| 7-13 Wiring HDL Modules Together | 493 | ||
| MOD-100 BCD Counter | 496 | ||
| 7-14 State Machines | 501 | ||
| Simulation of State Machines | 504 | ||
| Traffic Light Controller State Machine | 505 | ||
| Choosing HDL Coding Techniques | 511 | ||
| 7-15 Register Data Transfer | 513 | ||
| 7-16 IC Registers | 513 | ||
| Parallel In/Parallel Out—The 74ALS174/74HC174 | 514 | ||
| Serial In/Serial Out—The 74ALS166/74HC166 | 516 | ||
| Parallel In/Serial Out—The 74ALS165/74HC165 | 518 | ||
| Serial In/Parallel Out—The 74ALS164/74HC164 | 520 | ||
| 7-17 Shift-Register Counters | 522 | ||
| Ring Counter | 522 | ||
| Starting a Ring Counter | 522 | ||
| Johnson Counter | 523 | ||
| Decoding a Johnson Counter | 525 | ||
| IC Shift-Register Counters | 526 | ||
| 7-18 Troubleshooting | 526 | ||
| 7-19 Megafunction Registers | 529 | ||
| 7-20 HDL Registers | 533 | ||
| 7-21 HDL Ring Counters | 539 | ||
| 7-22 HDL One-Shots | 541 | ||
| Nonretriggerable One-Shot Simulation | 543 | ||
| Retriggerable, Edge-Triggered One-Shots in HDL | 544 | ||
| Edge-Triggered Retriggerable One-Shot Simulation | 547 | ||
| Chapter 8 Integrated-Circuit Logic Families | 570 | ||
| 8-1 Digital IC Terminology | 572 | ||
| Current and Voltage Parameters (See Figure 8-1) | 572 | ||
| Fan-Out | 573 | ||
| Propagation Delays | 574 | ||
| Power Requirements | 574 | ||
| Noise Immunity | 575 | ||
| Invalid Voltage Levels | 577 | ||
| Current-Sourcing and Current-Sinking Action | 577 | ||
| IC Packages | 578 | ||
| 8-2 The TTL Logic Family | 581 | ||
| Circuit Operation—LOW State | 581 | ||
| Circuit Operation—HIGH State | 582 | ||
| Current-Sinking Action | 584 | ||
| Current-Sourcing Action | 584 | ||
| Totem-Pole Output Circuit | 584 | ||
| TTL NOR Gate | 585 | ||
| Summary | 585 | ||
| 8-3 TTL Data Sheets | 586 | ||
| Supply Voltage and Temperature Range | 587 | ||
| Voltage Levels | 587 | ||
| Maximum Voltage Ratings | 588 | ||
| Power Dissipation | 588 | ||
| Propagation Delays | 588 | ||
| 8-4 TTL Series Characteristics | 589 | ||
| Standard TTL, 74 Series | 590 | ||
| Schottky TTL, 74S Series | 590 | ||
| Low-Power Schottky TTL, 74LS Series (LS-TTL) | 591 | ||
| Advanced Schottky TTL, 74AS Series (AS-TTL) | 591 | ||
| Advanced Low-Power Schottky TTL, 74ALS Series | 591 | ||
| 74F—Fast TTL | 591 | ||
| Comparison of TTL Series Characteristics | 592 | ||
| 8-5 TTL Loading and Fan-Out | 593 | ||
| Determining the Fan-Out | 594 | ||
| 8-6 Other TTL Characteristics | 598 | ||
| Unconnected Inputs (Floating) | 598 | ||
| Unused Inputs | 598 | ||
| Tied-Together Inputs | 599 | ||
| Biasing TTL Inputs Low | 600 | ||
| Current Transients | 601 | ||
| 8-7 MOS Technology | 602 | ||
| The MOSFET | 603 | ||
| Basic MOSFET Switch | 603 | ||
| 8-8 Complementary MOS Logic | 605 | ||
| CMOS Inverter | 606 | ||
| CMOS NAND Gate | 606 | ||
| CMOS NOR Gate | 607 | ||
| CMOS SET-RESET FF | 608 | ||
| 8-9 CMOS Series Characteristics | 608 | ||
| 4000/14000 Series | 608 | ||
| 74HC/HCT (High-Speed CMOS) | 609 | ||
| 74AC/ACT (Advanced CMOS) | 609 | ||
| 74AHC/AHCT (Advanced High-Speed CMOS) | 609 | ||
| BiCMOS 5-V Logic | 609 | ||
| Power-Supply Voltage | 610 | ||
| Logic Voltage Levels | 610 | ||
| Noise Margins | 610 | ||
| Power Dissipation | 611 | ||
| PD Increases with Frequency | 611 | ||
| Fan-Out | 612 | ||
| Switching Speed | 612 | ||
| Unused Inputs | 613 | ||
| Static Sensitivity | 613 | ||
| Latch-Up | 614 | ||
| 8-10 Low-Voltage Technology | 614 | ||
| CMOS Family | 615 | ||
| BiCMOS Family | 616 | ||
| 8-11 Open-Collector/Open-Drain Outputs | 617 | ||
| Open-Collector/Open-Drain Outputs | 618 | ||
| Open-Collector/Open-Drain Buffer/Drivers | 620 | ||
| IEEE/ANSI Symbol for Open-Collector/Drain Outputs | 621 | ||
| 8-12 Tristate (Three-State) Logic Outputs | 622 | ||
| Advantage of Tristate | 622 | ||
| Tristate Buffers | 623 | ||
| Tristate ICs | 625 | ||
| IEEE/ANSI Symbol for Tristate Outputs | 625 | ||
| 8-13 High-Speed Bus Interface Logic | 625 | ||
| 8-14 CMOS Transmission Gate (Bilateral Switch) | 627 | ||
| 8-15 IC Interfacing | 629 | ||
| Interfacing 5-V TTL and CMOS | 631 | ||
| CMOS Driving TTL | 632 | ||
| CMOS Driving TTL in the HIGH State | 632 | ||
| CMOS Driving TTL in the LOW State | 632 | ||
| 8-16 Mixed-Voltage Interfacing | 634 | ||
| Low-Voltage Outputs Driving High-Voltage Loads | 634 | ||
| High-Voltage Outputs Driving Low-Voltage Loads | 634 | ||
| 8-17 Analog Voltage Comparators | 636 | ||
| 8-18 Troubleshooting | 637 | ||
| Using a Logic Pulser and Probe to Test a Circuit | 638 | ||
| Finding Shorted Nodes | 638 | ||
| 8-19 Characteristics of an FPGA | 639 | ||
| Power-Supply Voltage | 639 | ||
| Logic Voltage Levels | 640 | ||
| Power Dissipation | 640 | ||
| Maximum Input Voltage and Output Current Ratings | 641 | ||
| Switching Speed | 641 | ||
| Chapter 9 MSI Logic Circuits | 658 | ||
| 9-1 Decoders | 659 | ||
| ENABLE Inputs | 660 | ||
| BCD-to-Decimal Decoders | 664 | ||
| BCD-to-Decimal Decoder/Driver | 665 | ||
| Decoder Applications | 665 | ||
| 9-2 BCD-to-7-Segment Decoder/Drivers | 667 | ||
| Common-Anode Versus Common-Cathode LED Displays | 668 | ||
| 9-3 Liquid-Crystal Displays | 669 | ||
| Driving an LCD | 670 | ||
| Types of LCDs | 671 | ||
| 9-4 Encoders | 673 | ||
| Priority Encoders | 675 | ||
| 74147 Decimal-to-BCD Priority Encoder | 675 | ||
| Switch Encoder | 676 | ||
| 9-5 Troubleshooting | 679 | ||
| 9-6 Multiplexers (Data Selectors) | 682 | ||
| Basic Two-Input Multiplexer | 683 | ||
| Eight-Input Multiplexer | 684 | ||
| Four-Input Multiplexer | 684 | ||
| Quad Two-Input MUX (74ALS157/HC157) | 686 | ||
| 9-7 Multiplexer Applications | 688 | ||
| Data Routing | 688 | ||
| Parallel-to-Serial Conversion | 689 | ||
| Operation Sequencing | 689 | ||
| Logic Function Generation | 692 | ||
| 9-8 Demultiplexers (Data Distributors) | 693 | ||
| 1-Line-to-8-Line Demultiplexer | 694 | ||
| Security Monitoring System | 695 | ||
| Synchronous Data Transmission System | 697 | ||
| Time Division Multiplexing | 699 | ||
| 9-9 More Troubleshooting | 703 | ||
| 9-10 Magnitude Comparator | 707 | ||
| Data Inputs | 708 | ||
| Outputs | 708 | ||
| Cascading Inputs | 708 | ||
| Applications | 709 | ||
| 9-11 Code Converters | 710 | ||
| Basic Idea | 711 | ||
| Conversion Process | 711 | ||
| Circuit Implementation | 712 | ||
| Other Code Converter Implementations | 714 | ||
| 9-12 Data Busing | 714 | ||
| 9-13 The 74ALS173/HC173 Tristate Register | 716 | ||
| 9-14 Data Bus Operation | 718 | ||
| Data Transfer Operation | 719 | ||
| Bus Signals | 720 | ||
| Simplified Bus Timing Diagram | 721 | ||
| Expanding the Bus | 721 | ||
| Simplified Bus Representation | 723 | ||
| Bidirectional Busing | 724 | ||
| 9-15 Decoders Using HDL | 725 | ||
| 9-16 The HDL 7-Segment Decoder/Driver | 729 | ||
| 9-17 Encoders Using HDL | 732 | ||
| 9-18 HDL Multiplexers and Demultiplexers | 736 | ||
| 9-19 HDL Magnitude Comparators | 740 | ||
| 9-20 HDL Code Converters | 741 | ||
| Chapter 10 Digital System Projects Using HDL | 764 | ||
| 10-1 Small-Project Management | 766 | ||
| Definition | 766 | ||
| Strategic Planning/Problem Decomposition | 766 | ||
| Synthesis and Testing | 767 | ||
| System Integration and Testing | 767 | ||
| 10-2 Stepper Motor Driver Project | 767 | ||
| Problem Definition | 768 | ||
| Strategic Planning/Problem Decomposition | 769 | ||
| Synthesis and Testing | 770 | ||
| 10-3 Keypad Encoder Project | 775 | ||
| Problem Analysis | 775 | ||
| Strategic Planning/Problem Decomposition | 777 | ||
| 10-4 Digital Clock Project | 781 | ||
| Top-Down Hierarchical Design | 784 | ||
| Building the Blocks from the Bottom Up | 786 | ||
| MOD-12 Design | 789 | ||
| Combining Blocks Graphically | 793 | ||
| Combining Blocks Using Only HDL | 794 | ||
| 10-5 Microwave Oven Project | 798 | ||
| Definition of the Project | 799 | ||
| Strategic Planning/Problem Decomposition | 800 | ||
| Synthesis/Integration and Testing | 804 | ||
| 10-6 Frequency Counter Project | 805 | ||
| Chapter 11 Interfacing with the Analog World | 814 | ||
| 11-1 Review of Digital Versus Analog | 815 | ||
| 11-2 Digital-to-Analog Conversion | 817 | ||
| Analog Output | 819 | ||
| Input Weights | 819 | ||
| Resolution (Step Size) | 820 | ||
| Percentage Resolution | 821 | ||
| What Does Resolution Mean? | 822 | ||
| Bipolar DACs | 824 | ||
| 11-3 DAC Circuitry | 824 | ||
| Conversion Accuracy | 826 | ||
| DAC with Current Output | 826 | ||
| R/2R Ladder | 828 | ||
| 11-4 DAC Specifications | 830 | ||
| Resolution | 830 | ||
| Accuracy | 830 | ||
| Offset Error | 831 | ||
| Settling Time | 831 | ||
| Monotonicity | 831 | ||
| 11-5 an Integrated-Circuit DAC | 832 | ||
| 11-6 DAC Applications | 833 | ||
| Control | 833 | ||
| Automatic Testing | 833 | ||
| Signal Reconstruction | 833 | ||
| A/D Conversion | 833 | ||
| Digital Amplitude Control | 833 | ||
| Serial DACs | 834 | ||
| 11-7 Troubleshooting DACs | 834 | ||
| 11-8 Analog-to-Digital Conversion | 836 | ||
| 11-9 Digital-Ramp ADC | 837 | ||
| A/D Resolution and Accuracy | 840 | ||
| Conversion Time, tC | 841 | ||
| 11-10 Data Acquisition | 842 | ||
| Reconstructing a Digitized Signal | 844 | ||
| Aliasing | 845 | ||
| Serial ADCs | 846 | ||
| 11-11 Successive-Approximation ADC | 846 | ||
| Conversion Time | 849 | ||
| An Actual IC: The ADC0804 Successive-Approximation ADC | 849 | ||
| 11-12 Flash ADCs | 854 | ||
| Conversion Time | 856 | ||
| 11-13 Other A/D Conversion Methods | 856 | ||
| Dual-Slope Integrating ADC | 857 | ||
| Voltage-to-Frequency ADC | 858 | ||
| Sigma/Delta Modulation | 858 | ||
| Pipelined ADC | 860 | ||
| 11-14 Typical ADC Architectures for Applications | 862 | ||
| 11-15 Sample-and-Hold Circuits | 863 | ||
| 11-16 Multiplexing | 864 | ||
| 11-17 Digital Signal Processing (DSP) | 865 | ||
| Digital Filtering | 866 | ||
| 11-18 Applications of Analog Interfacing | 869 | ||
| Data Acquisition Systems | 869 | ||
| Digital Camera | 870 | ||
| Digital Cellular Telephone | 870 | ||
| Chapter 12 Memory Devices | 886 | ||
| 12-1 Memory Terminology | 888 | ||
| 12-2 General Memory Operation | 892 | ||
| Address Inputs | 893 | ||
| The WE input | 893 | ||
| Output enable (OE) | 894 | ||
| Memory Enable | 894 | ||
| 12-3 CPU–Memory Connections | 895 | ||
| 12-4 Read-Only Memories | 897 | ||
| ROM Block Diagram | 897 | ||
| The Read Operation | 898 | ||
| 12-5 ROM Architecture | 899 | ||
| Output Buffers | 900 | ||
| Register Array | 900 | ||
| Address Decoders | 900 | ||
| 12-6 ROM Timing | 901 | ||
| 12-7 Types of ROMs | 902 | ||
| Mask-Programmed ROM | 903 | ||
| Programmable ROMs (PROMs) | 905 | ||
| Erasable Programmable ROM (EPROM) | 906 | ||
| Electrically Erasable PROM (EEPROM) | 907 | ||
| 12-8 Flash Memory | 909 | ||
| A Typical CMOS Flash Memory IC | 910 | ||
| Flash Technology: NOR and NAND | 911 | ||
| 12-9 ROM Applications | 914 | ||
| Embedded Microcontroller Program Memory | 914 | ||
| Data Transfer and Portability | 914 | ||
| Bootstrap Memory | 914 | ||
| Data Tables | 915 | ||
| Data Converter | 915 | ||
| Function Generator | 915 | ||
| 12-10 Semiconductor RAM | 916 | ||
| 12-11 RAM Architecture | 917 | ||
| Read Operation | 918 | ||
| Write Operation | 918 | ||
| Chip Select | 918 | ||
| Common Input/Output Pins | 918 | ||
| 12-12 Static RAM (SRAM) | 919 | ||
| Static-RAM Timing | 920 | ||
| Read Cycle | 920 | ||
| Write Cycle | 922 | ||
| 12-13 Dynamic RAM (DRAM) | 922 | ||
| 12-14 Dynamic RAM Structure and Operation | 924 | ||
| Address Multiplexing | 925 | ||
| 12-15 DRAM Read/Write Cycles | 929 | ||
| DRAM Read Cycle | 929 | ||
| DRAM Write Cycle | 930 | ||
| 12-16 DRAM Refreshing | 930 | ||
| 12-17 DRAM Technology | 933 | ||
| Memory Modules | 933 | ||
| FPM DRAM | 934 | ||
| EDO DRAM | 934 | ||
| SDRAM | 934 | ||
| DDRSDRAM | 934 | ||
| 12-18 Other Memory Technologies | 935 | ||
| Magnetic Storage | 935 | ||
| Optical Memory | 936 | ||
| Phase Change Ram (PRAM) | 937 | ||
| Ferroelectric RAM (FRAM) | 937 | ||
| 12-19 Expanding Word Size and Capacity | 937 | ||
| Expanding Word Size | 938 | ||
| Expanding Capacity | 940 | ||
| Incomplete Address Decoding | 943 | ||
| Combining DRAM Chips | 944 | ||
| 12-20 Special Memory Functions | 945 | ||
| Cache Memory | 946 | ||
| First-In, First-Out Memory (FIFO) | 947 | ||
| Circular Buffers | 948 | ||
| Chapter 13 Programmable Logic Device Architectures | 960 | ||
| 13-1 Digital Systems Family Tree | 962 | ||
| More on PLDs | 964 | ||
| 13-2 Fundamentals of PLD Circuitry | 968 | ||
| PLD Symbology | 969 | ||
| 13-3 PLD Architectures | 970 | ||
| PROMs | 970 | ||
| Programmable Array Logic (PAL) | 971 | ||
| Field Programmable Logic Array (FPLA) | 974 | ||
| Generic Array Logic (GAL) | 974 | ||
| 13-4 The Altera MAX and MAX II Families | 975 | ||
| 13-5 Generations of HCPLDs | 978 | ||
| Glossary | 982 | ||
| Answers to Selected Problems | 995 | ||
| index of ICs | 1003 | ||
| Index | 1006 |