BOOK
Logic and Computer Design Fundamentals, Global Edition
Morris R. Mano | Charles R. Kime | Tom Martin
(2016)
Additional Information
Book Details
Abstract
For courses in Logic and Computer design.
Understanding Logic and Computer Design for All Audiences
Logic and Computer Design Fundamentals is a thoroughly up-to-date text that makes logic design, digital system design, and computer design available to students of all levels. The Fifth Edition brings this widely recognized source to modern standards by ensuring that all information is relevant and contemporary. The material focuses on industry trends and successfully bridges the gap between the much higher levels of abstraction students in the field must work with today than in the past.
Broadly covering logic and computer design, Logic and Computer Design Fundamentals is a flexibly organized source material that allows instructors to tailor its use to a wide range of student audiences.
Table of Contents
| Section Title | Page | Action | Price |
|---|---|---|---|
| Cover | Cover | ||
| Logic and Computer Design Fundamentals | 1 | ||
| Copyright | 2 | ||
| Contents | 3 | ||
| Preface | 12 | ||
| Chapter 1: Digital Systems and Information | 19 | ||
| Information Representation | 20 | ||
| The Digital Computer | 22 | ||
| Beyond the Computer | 23 | ||
| More on the Generic Computer | 26 | ||
| Abstraction Layers in Computer Systems Design | 28 | ||
| An Overview of the Digital Design Process | 30 | ||
| Number Systems | 31 | ||
| Binary Numbers | 33 | ||
| Octal and Hexadecimal Numbers | 34 | ||
| Number Ranges | 36 | ||
| Arithmetic Operations | 36 | ||
| Conversion from Decimal to Other Bases | 39 | ||
| Decimal Codes | 41 | ||
| Alphanumeric Codes | 42 | ||
| ASCII Character Code | 42 | ||
| Parity Bit | 45 | ||
| Gray Codes | 46 | ||
| Chapter Summary | 48 | ||
| References | 49 | ||
| Problems | 49 | ||
| Chapter 2: Combinational Logic Circuits | 53 | ||
| Binary Logic and Gates | 54 | ||
| Binary Logic | 54 | ||
| Logic Gates | 56 | ||
| HDL Representations of Gates | 60 | ||
| Boolean Algebra | 61 | ||
| Basic Identities of Boolean Algebra | 65 | ||
| Algebraic Manipulation | 67 | ||
| Complement of a Function | 70 | ||
| Standard Forms | 71 | ||
| Minterms and Maxterms | 71 | ||
| Sum of Products | 75 | ||
| Product of Sums | 76 | ||
| Two-Level Circuit Optimization | 77 | ||
| Cost Criteria | 77 | ||
| Map Structures | 79 | ||
| Two-Variable Maps | 81 | ||
| Three-Variable Maps | 83 | ||
| Map Manipulation | 87 | ||
| Essential Prime Implicants | 87 | ||
| Nonessential Prime Implicants | 89 | ||
| Product-of-Sums Optimization | 90 | ||
| Don’t-Care Conditions | 91 | ||
| Exclusive-Or Operator and Gates | 94 | ||
| Odd Function | 94 | ||
| Gate Propagation Delay | 96 | ||
| HDLs Overview | 98 | ||
| Logic Synthesis | 100 | ||
| HDL Representations—VHDL | 102 | ||
| HDL Representations—Verilog | 110 | ||
| Chapter Summary | 117 | ||
| References | 118 | ||
| Problems | 118 | ||
| Chapter 3: Combinational Logic Design | 129 | ||
| Beginning Hierarchical Design | 130 | ||
| Technology Mapping | 134 | ||
| Combinational Functional Blocks | 138 | ||
| Rudimentary Logic Functions | 138 | ||
| Value-Fixing, Transferring, and Inverting | 139 | ||
| Multiple-Bit Functions | 139 | ||
| Enabling | 142 | ||
| Decoding | 144 | ||
| Decoder and Enabling Combinations | 148 | ||
| Decoder-Based Combinational Circuits | 151 | ||
| Encoding | 153 | ||
| Priority Encoder | 154 | ||
| Encoder Expansion | 155 | ||
| Selecting | 156 | ||
| Multiplexers | 156 | ||
| Multiplexer-Based Combinational Circuits | 166 | ||
| Iterative Combinational Circuits | 166 | ||
| Binary Adders | 173 | ||
| Half Adder | 173 | ||
| Full Adder | 174 | ||
| Binary Ripple Carry Adder | 175 | ||
| Binary Subtraction | 177 | ||
| Complements | 178 | ||
| Subtraction Using 2s Complement | 180 | ||
| Binary Adder-Subtractors | 181 | ||
| Signed Binary Numbers | 182 | ||
| Signed Binary Addition and Subtraction | 184 | ||
| Overflow | 186 | ||
| HDL Models of Adders | 188 | ||
| Behavioral Description | 190 | ||
| Other Arithmetic Functions | 193 | ||
| Contraction | 194 | ||
| Incrementing | 195 | ||
| Decrementing | 196 | ||
| Multiplication by Constants | 196 | ||
| Division by Constants | 198 | ||
| Zero Fill and Extension | 198 | ||
| Chapter Summary | 199 | ||
| References | 199 | ||
| Problems | 200 | ||
| Chapter 4: Sequential Circuits | 213 | ||
| Sequential Circuit Definitions | 214 | ||
| Latches | 217 | ||
| SR and SR Latches | 217 | ||
| D Latch | 220 | ||
| Flip-Flops | 220 | ||
| Edge-Triggered Flip-Flop | 222 | ||
| Standard Graphics Symbols | 223 | ||
| Direct Inputs | 225 | ||
| Sequential Circuit Analysis | 226 | ||
| Input Equations | 226 | ||
| State Table | 227 | ||
| State Diagram | 229 | ||
| Sequential Circuit Simulation | 232 | ||
| Sequential Circuit Design | 234 | ||
| Design Procedure | 234 | ||
| Finding State Diagrams and State Tables | 235 | ||
| State Assignment | 242 | ||
| Designing with D Flip-Flops | 243 | ||
| Designing with Unused States | 246 | ||
| Verification | 248 | ||
| State-Machine Diagrams and Applications | 250 | ||
| State-Machine Diagram Model | 252 | ||
| Constraints on Input Conditions | 254 | ||
| Design Applications Using State- Machine Diagrams | 256 | ||
| HDL Representation for Sequential Circuits—VHDL | 264 | ||
| HDL Representation for Sequential Circuits—Verilog | 273 | ||
| Flip-Flop Timing | 282 | ||
| Sequential Circuit Timing | 283 | ||
| Asynchronous Interactions | 286 | ||
| Synchronization and Metastability | 287 | ||
| Synchronous Circuit Pitfalls | 287 | ||
| Chapter Summary | 294 | ||
| References | 295 | ||
| Problems | 296 | ||
| Chapter 5: Digital Hardware Implementation | 311 | ||
| The Design Space | 311 | ||
| Integrated Circuits | 311 | ||
| CMOS Circuit Technology | 312 | ||
| Technology Parameters | 318 | ||
| Programmable Implementation Technologies | 320 | ||
| Read-Only Memory | 322 | ||
| Programmable Logic Array | 324 | ||
| Programmable Array Logic Devices | 327 | ||
| Field Programmable Gate Array | 329 | ||
| Chapter Summary | 334 | ||
| References | 334 | ||
| Problems | 334 | ||
| Chapter 6: Registers and Register Transfers | 339 | ||
| Registers and Load Enable | 340 | ||
| Register with Parallel Load | 341 | ||
| Register Transfers | 343 | ||
| Register Transfer Operations | 345 | ||
| Register Transfers in VHDL and Verilog | 347 | ||
| Microoperations | 348 | ||
| Arithmetic Microoperations | 349 | ||
| Logic Microoperations | 351 | ||
| Shift Microoperations | 353 | ||
| Microoperations on a Single Register | 353 | ||
| Multiplexer-Based Transfers | 354 | ||
| Shift Registers | 356 | ||
| Ripple Counter | 361 | ||
| Synchronous Binary Counters | 363 | ||
| Other Counters | 367 | ||
| Register-Cell Design | 370 | ||
| Multiplexer and Bus-Based Transfers for Multiple Registers | 375 | ||
| High-Impedance Outputs | 377 | ||
| Three-State Bus | 379 | ||
| Serial Transfer and Microoperations | 380 | ||
| Serial Addition | 381 | ||
| Control of Register Transfers | 383 | ||
| Design Procedure | 384 | ||
| HDL Representation for Shift Registers and Counters—VHDL | 400 | ||
| HDL Representation for Shift Registers and Counters—Verilog | 402 | ||
| Microprogrammed Control | 404 | ||
| Chapter Summary | 406 | ||
| References | 407 | ||
| Problems | 407 | ||
| Chapter 7: Memory Basics | 419 | ||
| Memory Definitions | 419 | ||
| Random-Access Memory | 420 | ||
| Write and Read Operations | 422 | ||
| Timing Waveforms | 423 | ||
| Properties of Memory | 425 | ||
| SRAM Integrated Circuits | 425 | ||
| Coincident Selection | 427 | ||
| Array of SRAM ICs | 431 | ||
| DRAM ICs | 434 | ||
| DRAM Cell | 435 | ||
| DRAM Bit Slice | 436 | ||
| DRAM Types | 440 | ||
| Synchronous DRAM (SDRAM) | 442 | ||
| Double-Data-Rate SDRAM (DDR SDRAM) | 444 | ||
| RAMBUS® DRAM (RDRAM) | 445 | ||
| Arrays of Dynamic RAM ICs | 446 | ||
| Chapter Summary | 446 | ||
| References | 447 | ||
| Problems | 447 | ||
| Chapter 8: Computer Design Basics | 449 | ||
| Introduction | 450 | ||
| Datapaths | 450 | ||
| The Arithmetic/Logic Unit | 453 | ||
| Arithmetic Circuit | 453 | ||
| Logic Circuit | 456 | ||
| Arithmetic/Logic Unit | 458 | ||
| The Shifter | 459 | ||
| Barrel Shifter | 460 | ||
| Datapath Representation | 461 | ||
| The Control Word | 463 | ||
| A Simple Computer Architecture | 469 | ||
| Instruction Set Architecture | 469 | ||
| Storage Resources | 470 | ||
| Instruction Formats | 471 | ||
| Instruction Specifications | 473 | ||
| Single-Cycle Hardwired Control | 476 | ||
| Instruction Decoder | 477 | ||
| Sample Instructions and Program | 479 | ||
| Single-Cycle Computer Issues | 482 | ||
| Multiple-Cycle Hardwired Control | 483 | ||
| Sequential Control Design | 487 | ||
| Chapter Summary | 492 | ||
| References | 494 | ||
| Problems | 494 | ||
| Chapter 9: Instruction Set Architecture | 501 | ||
| Computer Architecture Concepts | 501 | ||
| Basic Computer Operation Cycle | 503 | ||
| Register Set | 503 | ||
| Operand Addressing | 504 | ||
| Three-Address Instructions | 505 | ||
| Two-Address Instructions | 505 | ||
| One-Address Instructions | 506 | ||
| Zero- Address Instructions | 506 | ||
| Addressing Architectures | 507 | ||
| Addressing Modes | 510 | ||
| Implied Mode | 511 | ||
| Immediate Mode | 511 | ||
| Register and Register-Indirect Modes | 512 | ||
| Direct Addressing Mode | 512 | ||
| Indirect Addressing Mode | 513 | ||
| Relative Addressing Mode | 514 | ||
| Indexed Addressing Mode | 515 | ||
| Summary of Addressing Modes | 516 | ||
| Instruction Set Architectures | 517 | ||
| Data-Transfer Instructions | 518 | ||
| Stack Instructions | 518 | ||
| Independent versus Memory- Mapped I/O | 520 | ||
| Data-Manipulation Instructions | 521 | ||
| Arithmetic Instructions | 521 | ||
| Logical and Bit- Manipulation Instructions | 522 | ||
| Shift Instructions | 524 | ||
| Floating-Point Computations | 525 | ||
| Arithmetic Operations | 526 | ||
| Arithmetic Operations | 527 | ||
| Standard Operand Format | 528 | ||
| Program Control Instructions | 530 | ||
| Conditional Branch Instructions | 531 | ||
| Procedure Call and Return Instructions | 533 | ||
| Program Interrupt | 535 | ||
| Types of Interrupts | 536 | ||
| Processing External Interrupts | 537 | ||
| Chapter Summary | 538 | ||
| References | 539 | ||
| Problems | 539 | ||
| Chapter 10: Risc and Cisc Central Processing Units | 547 | ||
| Pipelined Datapath | 548 | ||
| Execution of Pipeline Microoperations | 552 | ||
| Pipelined Control | 553 | ||
| Pipeline Programming and Performance | 555 | ||
| The Reduced Instruction Set Computer | 557 | ||
| Instruction Set Architecture | 557 | ||
| Addressing Modes | 560 | ||
| Datapath Organization | 561 | ||
| Control Organization | 564 | ||
| Data Hazards | 566 | ||
| Control Hazards | 573 | ||
| The Complex Instruction Set Computer | 577 | ||
| ISA Modifications | 579 | ||
| Datapath Modifications | 580 | ||
| Control Unit Modifications | 582 | ||
| Microprogrammed Control | 583 | ||
| Microprograms for Complex Instructions | 585 | ||
| More on Design | 588 | ||
| Advanced CPU Concepts | 589 | ||
| Recent Architectural Innovations | 592 | ||
| Chapter Summary | 595 | ||
| References | 596 | ||
| Problems | 597 | ||
| Chapter 11: Input—Output and Communication | 601 | ||
| Computer I/O | 601 | ||
| Sample Peripherals | 602 | ||
| Keyboard | 602 | ||
| Hard Drive | 603 | ||
| Liquid Crystal Display Screen | 605 | ||
| I/O Transfer Rates | 608 | ||
| I/O Interfaces | 608 | ||
| I/O Bus and Interface Unit | 609 | ||
| Example of I/O Interface | 610 | ||
| Strobing | 611 | ||
| Handshaking | 613 | ||
| Serial Communication | 614 | ||
| Synchronous Transmission | 615 | ||
| The Keyboard Revisited | 616 | ||
| A Packet-Based Serial I/O Bus | 617 | ||
| Modes of Transfer | 620 | ||
| Example of Program-Controlled Transfer | 621 | ||
| Interrupt-Initiated Transfer | 622 | ||
| Priority Interrupt | 624 | ||
| Daisy Chain Priority | 624 | ||
| Parallel Priority Hardware | 626 | ||
| Direct Memory Access | 627 | ||
| DMA Controller | 628 | ||
| DMA Transfe | 630 | ||
| Chapter Summary | 631 | ||
| References | 631 | ||
| Problems | 632 | ||
| Chapter 12: Memory Systems | 635 | ||
| Memory Hierarchy | 635 | ||
| Locality of Reference | 638 | ||
| Cache Memory | 640 | ||
| Cache Mappings | 642 | ||
| Line Size | 647 | ||
| Cache Loading | 648 | ||
| Write Methods | 649 | ||
| Integration of Concepts | 650 | ||
| Instruction and Data Caches | 652 | ||
| Multiple-Level Caches | 653 | ||
| Virtual Memory | 653 | ||
| Page Tables | 655 | ||
| Translation Lookaside Buffer | 657 | ||
| Virtual Memory and Cache | 659 | ||
| Chapter Summary | 659 | ||
| References | 660 | ||
| Problems | 660 | ||
| Index | 664 |